Detecting circuit for indicating occurrence of peak in an input signal

ABSTRACT

A circuit for processing an input signal incorporating a technique of constant fraction timing on the trailing edge of the input signal. The processing is performed in such a manner that the resultant timing signal is independent of the pulse shape and further incorporates means for adjusting the level at which the timing signal is derived in order to optimized the statistical or rms noise uncertainty and further serves to minimize the time delay from the peak of the input signal.

United States Patent 1191 Nutt 1 1 Jan. 30, 1973 1541 DETECTING CIRCUITFOR 3,553,593 1/1971 Gedance .328/116 x INDICATING OCCURRENC OF PEAK3,564,287 2/1971 Todd ..328/151 x IN AN INPUT SIGNAL [75] Inventor:Ronald Nutt, Knoxville, Tenn.

[73] Assignee: Ortec, Incorporated, Oak Ridge,

Tenn. i

[221 Filed: July 9,1970

[21] Appl. No.: 53,359

[52] U.S. Cl. ..307/235, 328/116, 328/146, 328/151, 330/30 D [51} Int.Cl. ..Il03k 5/20 [581 Field of Search ..307/235;328/11S,116,117,

References Cited OTHER PUBLICATIONS Bjorkman and Brondum, Peak Pickingand Noise Suppression Circuitry, IBM Technical Disclosure Bulletin, Vol.9, No. 6, Nov. 1966 p. 508-589.

Primary ExaminerDonald D. Forrer Assistant ExaminerR. C. WoodbridgeAttorney-Ralph L. Cadwallader and Lawrence P. Benjamin 5? ABSTRACT Acircuit for processing an input signal incorporating a technique ofconstant fraction timing on the trailing edge of the input signal. Theprocessing is performed in such a manner that the resultant timingsignal is independent of the pulse shape and further incorporates meansfor adjusting the level at which the timing signal is derived in orderto optimized the statistical or rms noise uncertainty and further servesto minimize the time delay from the peak of the input signal.

7 Claims, 2 Drawing Figures STRETCHER CIRCUIT AMPLIFIER d T swn'cu A)oeriacroa7 V AT G 34 LQ UNITY GAIN AMPLIFIER PATENTED JAN 30 I973 SHEET1 BF 2 .CDUEQ mmIuPwmhm H mokowkuo RONALD NUTT INVENTOR ATTORNEYSPATENTEUJAN 30 ms 3,714,464 SHEET 20F 2 RONALD NUTT INVENTOR ATTORNEYSDETECTING CIRCUIT FOR INDICATING OCCURRENCE OF PEAK IN AN INPUT SIGNALBACKGROUNDOF THE INVENTION proposed signal processing circuit thatdistinguishes it from other techniques used in conjunction with timingsingle channel analyzers. A system based on the premise ofconstantfraction timing on the trailing edge is useful for all shapes of signalpulses having either single polarity or bipolar shape in that thesystematic timing error may essentially be reduced to zero, for all suchsignal shapes so long as the signal bandwidth is constant.

The ability to adjust the fraction of pulse height offers at least threeunique advantages. First, a large class ofsignals may be used, having anoptimum trigger point which is equal to a fraction of the peakamplitude. For such signals the timing fraction can be adjusted tooptimize the time resolutions. Secondly, in many applications the signalcountrate is sufficiently high that pairs of signal pulses can occurvery close together. For such applications the constant fraction can beadjusted to minimize the pulse pair resolving time. The third advantageof the variable constant fraction is that the time delay from the peakof the pulse can be minimized for the applications where this is animportant parameter. In general, it is believed that this is the firsttime adjustable constant fraction that has been used on the trailingedge ofthe signal pulse.

The time derivation process described has applications in many fieldswhere an electrical signal, in the form of a voltage pulse, is to beanalyzed for both time and amplitude information. For example, in thenuclear field, the signals derived from a scintillation detector orsolid state detector contains information about when incident radiationreaches the detector as well as the magnitude (amplitude) or amount ofthe radiation. The proposed circuit, when used in conjunction with asingle channel analyzer, establishes both the time and the amplitudeinformation. THe use of a constant fraction timing technique based onthe trailing edge of such signals would offer all the previouslymentioned advantages over prior art techniques.

The purpose of performing the timing on the trailing edge is to allowsufficient time for decisions to be made on pulse peaks. The proposedconstant fraction technique, for all practical purposes, almost entirelyeliminates systematic timing errors due to pulse height variations. Thefraction of the pulse height on which the timing is performed may beadjusted to obtain optimum time resolution due to noise or statisticalcontributions, and minimum time delay from the peak of the input signal.

SUMMARY OF THE INVENTION state, in the absence of an input signal, thecomparator is, for example, in a high" state. However, when the signallevel becomes more positive than a reference signal connected to thecomparator state, the comparators output will switch from the high stateto a low state. The low state of the comparator then causes another gateto switch the comparator reference to a voltage level that is derivedfrom the stretcher circuit. During this interval, the stretcher circuitis measuring the peak amplitude of the input signal and storing thisinformation on a capacitor. Thus, the information stored in thecapacitor which has been switched to the gate, is equal to a constantfraction of the input pulse height. The comparator remains in the lowstate until the signal becomes less positive than the voltage stored onthe capacitor at which time the output of the comparator is switched tothe high state and a timing marker is generated.

It is, therefore, one object of the present invention to provide acircuit capable of producing a timing pulse based on a constant fractionof the trailing edge of an input signal.

Still another object of the present invention is to provide a circuitcapable of producing a timing pulse based on a constant fraction of thetrailing edge of an input signal wherein the systematic timing error maybe essentially reduced to zero for all such signal shapes having anapproximately constant bandwidth.

The features of my invention which I believe to be novel are set forthwith particularity in the appended claims. My invention itself, however,both as to its or ganization and method of operation, together withfurther objects and advantages thereof, may be best understood byreference to the following description taken in conjunction with theaccompanying drawings.

DESCRIPTION or THE DRAWINGS FIG. 1 is a partial schematic and blockdiagram of my signal processing circuit; and

FIG. 2 is a schematic circuit diagram of one embodiment ofa completetiming generator.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. I there isshown an input terminal 10 for applying an input signal to a bufferamplifier 42 the output of which is applied simultaneously topotentiometer 26 and to comparator 14. The voltage developed acrosspotentiometer 26 is applied as one input to a stretcher circuitconsisting of amplifiers 20 and 22 having a series diode 28 and a shuntcapacitor 30 connected between the amplifiers. Shunt capacitor 30 has agate circuit 38 connected parallel therewith and a lead 44 connected toone output of gate 46. The output of amplifier 22 is applied as an inputto amplifier 20, by means of lead 40, and also as an input to gate 16 bymeans of lead 36. Reference voltage 32 is applied as another input togate 16 by means of lead 34.

Referring now to FIG. 2 there is shown a complete circuit diagram of anembodiment of my invention. In the operation of my device, a positivegoing input signal is applied to input terminal 10 which signal is thenapplied as an input to buffer amplifier 42, consisting of active devicesQ1 through 04 arranged in a typical buffer configuration. The outputofbuffer amplifier 42 is applied, as an input, to terminal 3 of'anintegrated circuit (IC) arranged as a comparator. In this particularsituation, while I have choosen to use and show a devices 011-015 withthe input thereto being shown as a pair of N-channel field effecttransistors (FET). While FETs Q11 and Q12 are shown in a differentialamplifier configuration, it will be obvious to those skilled in the artthat various other types of active devices may be substituted for 011and Q12.

The output of comparator 14 is then applied as an input to gate 46consisting of Q5, Q6 and Q24 and the cathode terminal of Zener diode D1,the anode terminal of which is connected directly to tithing outputterminal 18.

"The output of amplifier 20 is applied as an input to unity gainamplifier 22 through a series diode 28 arranged with its anode terminalconnected to amplifier 20 and its cathode terminal connected toamplifier 22. Amplifier 22 consist of active devices 018 Q23. Connectedbetween the cathode end of diode 28 and ground is capacitor 30, thefunction of which will be described hereinafter.

The output of unity gain amplifier 22 is derived at the emitterelectrode of active device Q23 and is applied to the gate of PET Q12 bymeans of lead 40 to provide a feedback loop for the stretcher circuit.Lead 36 is connected to the junction of the gate of PET Q12 and thefeedback loop, designated by lead 40, so as to provide one input to gate16. Another input to gate 16 is provided by potentiometer 32 between asource of operating potential and ground and is applied by means of lead34 to the base ofactive device 010.

Clamp 38 consists of active devices Q16 and 017.

which are connected in parallel with capacitor 30 and is provided withan input thereto, by means of lead 44, representing one output ofdetector 46.

, The gate circuit that detects the particular reference signal to beapplied to pin 2 of comparator 14 involves active devices 05 Q (indetector 46 and gate 16). When comparator 14 is in a quiescent state,that is, with no signal applied to input terminal 10, it may be said tobe in a high state ==+2.5 volts) in which event,

transistors 05, Q9 and 010 will be biased ON and a reference voltage, (Ecorresponding to the leading edge of the input signal (derived acrossresistor 32) is applied to pin 2 by means of active devices 010 and Q9.Any incoming signal appearing at input terminal 10, will switchcomparator 14 to a low state =0.5

volts), in which event, active devices 05, Q9 and Q10 switch to an OFFcondition and active devices Q6 and Q7 and 08 are then switched ON. Whenthis latter condition occurs, the reference voltage derived from lead 36is applied to pin 2 by means of active devices Q7 and This latterreference voltage (E is obtained from the peak detector and stretchercircuits (20, 22). The incoming attenuated input signal is applied tothe differential pair Q11 and Q12 (by meansof potentiometer 26) thuscausing active devices 014 and Q15 to be switched ON allowing capacitor30 to be charged to a positive voltage. Capacitor 30 continues to becharged until the peak of the signal is reached at which time, a voltageequal to the capacitor voltage appears at the output of unity gainamplifier 22 and is fed back to the other input (the gate of 012) of thedifferential pair 011 and Q12. After the peak is reached and the signalis slightly less than the peak voltage, diode 28 is reversed biasedcausing the charge on capacitor 30 to be stored as it no longer has aleakage path. When this occurs,.the voltage at the output of unity gainamplifier 22 becomes greater than the signal applied to the gate of 011and the differential pair (011 and Q12) are switched OFF. Thus, when thevoltage stored on capacitor 30 appears at the emitter of active deviceQ23 (in unity gain amplifier 22) it will be proportional to the peak ofthe input signal. In this manner, the signal previously referred to asreference signal E is applied as one input to pin 2 of comparator 14 togenerate a timing signal or marker. Thus, when a timing signal isgenerated and applied to output terminal 18 the timing pulse is applied,by means of lead 44, as an input to Q17 of clamp 38 to restore thevoltage on capacitor 30 to zero, signifying that the processing iscompleted.

While I have described what is presently considered the preferredembodiment of my invention, it will be obvious to those skilled in theart that various other changes and modifications may be made thereinwithout departing from the inventive concept, and it is aimed,therefore, to cover all such changes and modifications that may fallwithin the true spirit and scope of my invention.

What is claimed is:

1. A circuit for detecting an input signal and producing an outputsignal to indicate the occurrence of a peak in the inputsignal,comprising:

a comparator having first and second inputs and an output, said firstinput being responsive to the input signal;

a stretcher circuit having an input responsive to the input signal andan output for producing a signal proportional to the peak amplitude ofthe input signal; and

means for applying a predetermined reference voltage to the second inputof said comparator while the, amplitude of the input signal is less thanthe reference voltage and forapplying the signal produced by saidstretcher circuit to the second input of said comparator when theamplitude of the input signal exceeds the reference voltage, the outputof said comparator thereafter changing state when the amplitude of theinput signal decreases to the amplitude of the signal produced by saidstretcher circuit to indicate the occurrence of a peak in the inputsignal.

2. The circuit of claim 1, wherein said means comprises:

a source for generating a predetermined reference voltage;and

a gating circuit having a first input responsive to the output of saidcomparator, a second input for receiving the predetermined referencevoltage from said source, a third input responsive to the output of saidstretcher circuit, and an output coupled to the second input of saidcomparator for selectively applying the predetermined reference voltageand the signal produced by said stretcher circuit to the second input ofsaid comparator in response to signals produced by said comparator.

3. The circuit ofclaim l, which includes:

a buffer amplifier having an input responsive to the input signal and anoutput coupled to the first input of said comparator and the inputof-said stretcher circuit.

4. The circuit of claim 1, which includes:

a potentiometer coupled to the input of said stretcher circuit andresponsive to the input signal for applying a signal proportional to theinput signal to said stretchercircuit.

5. The circuit of claim 1, wherein said stretcher circuit comprises:

a first amplifier having an input responsive to the input signal and anoutput;

a second amplifier having an input and an output;

a diode having an anode terminal connected to the output of said firstamplifier and a cathode terminal connected to the input of said secondamplifier; and i a capacitance responsive to the cathode terminal ofsaid diode for storing a signal proportional to the peak amplitude ofthe input signal.

6. The circuit ofclaim 5, which includes:

a switch connected in parallel with said capacitance and responsive tothe output of said comparator for discharging said capacitance when theinput signal at the first input of said comparator is less than thesignal applied to its second input.

7. The circuit of claim 6, wherein said means responsive to the outputof said comparator comprises:

a source for generating a predetermined reference voltage, and

a gating circuit having a first input responsive to the output of saidcomparator, a second input for receiving the predetermined referencevoltage from said source, a third input responsive to the output of saidsecond amplifier in said stretcher circuit, and an output coupled to thesecond input of said comparator for selectively applying thepredetermined reference voltage and the signal produced by saidstretcher circuit to the second input of said comparator: and whichincludes a detector responsive to the output of said comparator forcontrolling the operation of said gating circuit to apply the referencevoltage to the second input of said comparator while the amplitude ofthe input signal is less than the reference voltage and to apply theoutput signal produced by said stretcher circuit to the second input ofthe comparator when the amplitude of the input signal exceeds thereference voltage and for operating said switch to discharge saidcapacitance when the input signal is less than the signal applied to thesecond input of said comparator.

1. A circuit for detecting an input signal and producing an outputsignal to indicate the occurrence of a peak in the input signal,comprising: a comparator having first and second inputs and an output,said first input being responsive to the input signal; a stretchercircuit having an input responsive to the input signal and an output forproducing a signal proportional to the peak amplitude of the inputsignal; and means for applying a predetermined reference voltage to thesecond input of said comparator while the amplitude of the input signalis less than the reference voltage and for applying the signal producedby said stretcher circuit to the second input of said comparator whenthe amplitude of the input signal exceeds the reference voltage, theoutput of said comparator thereafter changing state when the amplitudeof the input signal decreases to the amplitude of the signal produced bysaid stretcher circuit to indicate the occurrence of a peak in the inputsignal.
 1. A circuit for detecting an input signal and producing anoutput signal to indicate the occurrence of a peak in the input signal,comprising: a comparator having first and second inputs and an output,said first input being responsive to the input signal; a stretchercircuit having an input responsive to the input signal and an output forproducing a signal proportional to the peak amplitude of the inputsignal; and means for applying a predetermined reference voltage to thesecond input of said comparator while the amplitude of the input signalis less than the reference voltage and for applying the signal producedby said stretcher circuit to the second input of said comparator whenthe amplitude of the input signal exceeds the reference voltage, theoutput of said comparator thereafter changing state when the amplitudeof the input signal decreases to the amplitude of the signal produced bysaid stretcher circuit to indicate the occurrence of a peak in the inputsignal.
 2. The circuit of claim 1, wherein said means comprises: asource for generating a predetermined reference voltage; and a gatingcircuit having a first input responsive to the output of saidcomparator, a second input for receiving the predetermined referencevoltage from said source, a third input responsive to the output of saidstretcher circuit, and an output coupled to the second input of saidcomparator for selectively applying the predetermined reference voltageand the signal produced by said stretcher circuit to the second input ofsaid comparator in response to signals produced by said comparator. 3.The circuit of claim 1, which includes: a buffer amplifier having aninput responsive to the input signal and an output coupled to the firstinput of said comparator and the input of said stretcher circuit.
 4. Thecircuit of claim 1, which includes: a potentiometer coupled to the inputof said stretcher circuit and responsive to the input signal forapplying a signal proportional to the input signal to said stretchercircuit.
 5. The circuit of claim 1, wherein said stretcher circuitcomprises: a first amplifier having an input responsive to the inputsignal and an output; a second amplifier having an input and an output;a diode having an anode terminal connected to the output of said firstamplifier and a cathode terminal connected to the input of said secondamplifier; and a capacitance responsive to the cathode terminal of saiddiode for storing a signal proportional to the peak amplitude of theinput signal.
 6. The circuit of claim 5, which includes: a switchconnected in parallel with said capacitance and responsive to the outputof said comparator for discharging said capacitance when the inputsignal at the first input of said comparator is less than the signalapplied to its second input.